The move to the 450-mm wafer size has garnered an increasing amount of interest in the semiconductor manufacturing industry as many suppliers have pushed back at making the shift, arguing that there is still much to be gained in terms of efficiency from the 300-mm wafer size, as well as high development costs.
By Ann Steffora Mutschler, Senior Editor — Electronic News, 6/13/2008
SAN FRANCISCO — During a Semiconductor Industry Association (SIA) roundtable on the future of Moore’s Law held here Thursday, Dr. Paolo Gargini, Intel fellow and director of technology strategy, said with regard to the continuing dialog on the move to the 450-mm wafer size, “From a technical point of view, this is not really very difficult, to be honest.”
“We’ve gone through several of these transitions and actually if you look at the situation nowadays, 90% of the steps are one wafer at a time, so the difficulty in the past was when you had to do diffusion on 100 wafers, and getting the wafers into the furnace was extremely complicated,” Gargini (pictured left) commented.
Indeed, this issue has garnered an increasing amount of interest in the semiconductor manufacturing industry as many suppliers have pushed back at making the shift, arguing that there is still much to be gained in terms of efficiency from the 300-mm wafer size. In January, industry analysts predicted the shift to 450-mm wafers would likely happen in 2025. However, in May, industry giants Intel, TSMC and Samsung said they had reached agreement that the industry needs to start working together to transition to the 450-mm wafer size, with the intention is to target 2012 to start a 450-mm pilot line.
Still, Gargini asserted, “If you have a chamber this big and make it bigger, and you put a bigger wafer in, you do some adjustments, but it is as simple as that. If you look also at the complexity of the equipment, it by in large relates – and I’m oversimplifying — to more steel and more massive structures, but it’s not extremely complicated from a technical point of view.
“It comes every eight, nine, 10 years and it is somewhat disruptive because everybody is used to doing two year improvement on equipment. So this appears like a destruction of this process, and you cannot do it by using a single supplier – you have to do it with the whole industry. In that case, it becomes more complicated. In fact, normally it takes four or five years of discussion. If I go back to 300-mm, we began discussing around 1993. By 1996 we got organized, by 1998 we had the right prototypes, and by 2001 it went into manufacturing. So we’ve already spent the down payment — the first two or three years of argument — which is always the same: The suppliers don’t want to do it, and we say that it’s good for you in the long run,” he continued.
Gargini noted that now as Intel and other industry players examine the complexity on each piece of fab equipment, much of the work that was done for the 300-mm wafer node can be utilized, citing fab automation as one example. “We already decided to reuse all the automation and the automation companies have not expressed too many concerns,” he said, and added that the public position and the private position of the equipment makers are not always the same. He said progress is actually being made.
In fact, last November, Tokyo-based Nikko Materials Co. Ltd. developed a 450-mm polycrystalline silicon wafer aimed at handling and mechanical testing, according to Gartner Dataquest
What is the cost comprised of?
“The early transitions were always stimulated by the suppliers because at that time, you used to have a wet bench, you make it a little bigger, you make the wafers a little bigger — it wasn’t very challenging. Only when we got to around the 6-inch wafer size did it become more complicated and at that point, Intel and IBM made an attempt to drive this convergence but it became clear that you can not drive in a vacuum. So 300-mm was a really good example of how to do this,” Gargini explained.
“The complexity came by doing two things at the same time: changing the technology node and changing the wafer size. By compounding this, then you multiply the complexity. But like what we experienced with the 300-mm generation, we established the process on 200-mm then we began – slower than the suppliers would have liked – the transition to 300-mm to make sure the processes were compatible,” he continued.
With costs estimated between less than $10 billion in a best case scenario to more than $1 trillion in a worst case scenario, according to Dan Hutcheson, president of VLSI Research, the topic is understandably a touchy one for many industry players.
“My opinion is that the compatibility between 300- and 450-mm will be even higher because everything now is down to a single wafer at a time that makes the scalability a much easier problem. Many people have memory of 10 years ago and that’s why this process happens only so often. You have to bridge 10 years of lack of dialog. … In my opinion, [the semiconductor equipment suppliers] are way overestimating the cost, Gargini concluded.
Lucas van Grinsven, director of corporate communications at Veldhoven, the Netherlands-based lithography leader ASML Holding NV, disagrees that the transition to the 450-mm wafer size is relatively easy. “I know quite a few people who would disagree,” he said in a one-on-one interview with Electronic News. “Officially, we haven’t made exact calculations … but it is a significant investment on behalf of the equipment makers. There is no doubt. I would disagree with Intel if they say it is a relatively simple transition because it is not. It’s a very complicated transition as was the transition from 200- to 300-mm.”
Further, he said, “Is it a demanding transition and one that will require a lot of attention from the equipment industry and ASML in particular? Yes. What is our position? If the market really says we want to move to 450-mm, we’ll move with them. So far, its not entirely clear what the position of the entire market is. … It will cost a lot of money. If the device makers are serious about this transition, they have to be committed to help fund the R&D that will have to be done.”
In terms of whether ASML thinks the 2012 pilot line date is feasible, van Grinsven did not say directly but commented, “We’ve got a lot of stuff on our plate at the moment, so we’re really busy already. We’ll have to see.”
Not to minimize the task, he concluded, “Obviously there is an efficiency gain to be had with the move from 300- to 450-mm and part of the industry discussion is about how much that gain will be. If you still have to expose every field, is that gain going to be 30% for lithography? Probably not. The gain will be elsewhere in the fab. Fundamentally, we believe the biggest gains are going to be had in the shrink, basically in continuing Moore’s Law. We’ve got an extended roadmap which will lead to much bigger efficiencies than 30% maximum for lithography.”