Making it as a mixed-signal foundry: Jazz Semiconductor seeks a strategy – Practical Chip Design – Blog on EDN – 1690000169

Making it as a mixed-signal foundry: Jazz Semiconductor seeks a strategy

Sep 13 2007 5:37PM | Permalink | Email this | Comments (0) |
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Coming up with a successful business model for a small mixed-signal foundry in a world where TSMC, UMC, IBM, Chartered, and Samsung are all touting mixed-signal and RF capabilities is a non-trivial exercise. If you can’t take on the big guns directly, you risk having to take on the artificially low cost structures of the second-tier fabs in the People’s Republic, with disastrous consequences for margins. So it is vital that there be some niche between the offerings of the huge tier-one foundries and the hungry ghosts of tier-two.

The most obvious way to create such a niche is with process specialization, as is being attempted by Malaysia’s Silterra, which we discussed recently. But this week another small specialty foundry, Jazz Semiconductor, outlined a quite different alternative.

The impetus for this strategy appears to have come from the company’s new investor, chairman and CEO, long-time Silicon Valley executive Gil Amelio. According to Chuck Fox, the former Keyeye CEO whom Amelio recruited to manage sales and marketing at Jazz, Amelio saw unrecognized value in the company if it could provide a new value proposition to customers. And that proposition needed to be based not just on process expertise—increasingly hard to differentiate today—but on the way the foundry interfaced to the customer’s design team.

Fox said that even today, the standard practice for best-of-breed analog and RF design is to create a design, tape it out, characterize the silicon, and iterate until the circuit is finally within specs. For all the reasons too obvious to repeat here, this is increasingly intractable for most companies. But can it really be changed?

Jazz is betting that it can. Marco Racanelli, vice president of technology and engineering at the company, believes it is possible to establish a new design interface, based not on test chips, but on statistical models that are connected directly to process-control data.

Establishing an interface between the process engineers and a group of analog or RF designers has been a persistent problem. If you establish the interface at too high a level, say by creating a library of parameterized functional blocks, you are intruding into the designers’ necessary flexibility. But if you provide a library of devices with incomplete or approximately-correct models, you are only giving chip designers enough information to generate their own test chips.

Jazz will try to get past this dilemma with a three-step process. The first step, already taken, is to build a set of parameterized device models that are directly connected to the process’s APC database. Designers can literally get on a Web site and calibrate their models for any specific wafer that has been completed, according to Racanelli. The second step will be to make this connection statistical, so that designers can see the distribution of variations in a model’s electrical parameters for a given run of wafers. This will allow, for instance, locating a process corner a known number of standard deviations from the mean of an electrical parameter, rather than at some relatively arbitrary worst-case point, established six months ago when a modeling engineer was last working on the device model.

Finally, Jazz hopes to provide a tool suite that will allow designers not merely to look at model statistics, but to use those models on a device-by-device basis to compose full circuit models, and use them in statistical and Monte-Carlo analyses of their designs. The hope is that by providing this much support for the device models, and by tying them directly to process data records, skilled design teams will be able to expect first-time-working silicon, rather than expecting a series of spins.

Further down the road, Racanelli says, Jazz is looking at raising the level of abstraction—but carefully. The company is examining analog design practice to identify primitives—such as gain cells, for example—that are widely used, relatively standard in structure and function, but are not part of the secret sauce for master analog designers. The hope is that Jazz can identify and build a library of such elements, and provide process-based, parameterized models for them as well. This could significantly accelerate detailed analog design without, it is hoped, compromising on the goal of first-time-working silicon. It is a challenging undertaking.